1. Field of the Invention
The present invention relates to a CMOS image sensor integrated with a static random access memory (SRAM), and more particularly, to a CMOS image sensor integrated with a one-transistor static random access memory (1T-SRAM) of ultra-density.
2. Description of the Prior Art
Complementary metal-oxide semiconductor (CMOS) image sensors are produced by using conventional semiconductor techniques, which can fabricate the image sensor and the related peripheral circuit simultaneously. When compared with a charge-coupled device (CCD), which requires 30 to 40 mask processes during manufacture, the CMOS image sensor only requires approximately 20 mask processes. CMOS sensors not only simplify the manufacturing process, but also reduce cost. In addition, CMOS image sensors have advantages of small size, high quantum efficiency, and low read-out noise.
However, since memory, such as dynamic random access memory (DRAM) and image sensor devices are manufactured on different chips, miniaturization of the image system is difficult. U.S. Pat. No. 6,563,187 teaches a CMOS image sensor, and particularly, a CMOS image sensor integrated with image sensor devices, a related signal processing circuit, and memory, such as DRAM or SRAM to reduce the cost and the power consumption.
However, a typical DRAM has to check a voltage on its capacitor periodically, and needs to charge or discharge in order to refresh the capacitor. In addition, if the image sensor is integrated with an SRAM comprising 4 to 6 transistors, it will have an area of more than 4 times the area of an image sensor integrated with a DRAM. The result is a reduced integrity, and a less than compact size. Additionally, the method disclosed in the '187 patent is to integrate the memory after all the logic devices have been formed. Such a process is overly complicated.